Online Interactive Session on Solvnet Helpdesk by Synopsys Team- Reg.

The Session will cover the following topic's:

• How to register on SolvNet.
• Locating the SITE ID on SolvNet.
• How to raise a support ticket on SolvNet for various issues (e.g., tool download, tool features related, design support related, etc.)
• Accessing documentation for any Synopsys product on SolvNet.
• Locating tool binaries, SCL, and other related resources.
• Accessing SAED PDKs.
• Finding training content (including self-paced and university curriculum modules)

Online Session on extraction of layers for the Die GDS package bonding by SCL Team - Reg

Technical (Online) Session on Post-Silicon Validation, Characterization, Testing, and Packaging Services by Tessolve for C2S Participants

The Session will cover the following topics:

• Overview of Tessolve and Post Si Support Flow.
• Capabilities in Test Engineering
• Bench Characterization Capabilities
• Overview of Product Engineering
• Introduction to Qualification
• Expertise in PCB Engineering
• Capabilities in Packaging
• Q & A and support for C2S participants.

Smarter Semiconductor Validation to Production: A Platform Approach with Emerson T&M

The Session will cover the following topics:

• Overview of Emerson T&M( Formerly NI)
• Introduction to platform based approach
• Automated Device Validation(ADV) workflows for pre and post silicon validation
• Use cases and solutions for ADV for Power and Performance Measurements, PMICs, ADCs, DACs and RF ICs
• Automated Production Test (APT) with NI Platform
• Q&A

Online Webinar Series Engineering Tomorrow: Launch your Semiconductor Career with Siemens EDA

The Session will cover the following topics:

• To build awareness around Electronic Design Automation (EDA) technologies and highlight how Siemens EDA's industry-leading products are shaping the future of semiconductor and electronic design

• A foundational element of design verification involves establishing correctness by construction, which will be explored through the Design Linting process. This will be succeeded by a discussion on the imperative for robust clock domain and reset domain crossings implementation and verification.
• The session will then transition to an exploration of Formal Verification technologies. These are emerging as a potent solution, facilitating early design analysis independent of testbench development. We will elucidate how formal verification contributes to mathematically proven design correctness, exhaustive verification coverage, and the early identification of corner-case scenarios.

Technical Online Session on IC Packaging: Trends & Challenges by Cadence Team

The Session details will be shared shortly

Beyond VLSI -Unveiling the Critical Role of PCB and IC Package Design in Modern Electronics

This Session provides a foundational understanding of IC Packaging and PCB Design.

• We will explore the electrical complexities of PCB & IC Package design in the context of high-performance systems and challenges involved around them. Participants will gain insights into leveraging PCB design and analysis tools, learning how to navigate manufacturability challenges and apply industry-leading best practices. The session will also showcase how sophisticated design platforms, such as Xpedition, can revolutionize design flow management.
• Furthermore, we'll explore the fundamental principles of Signal and Power Integrity in the context of both PCB and IC Packaging, demonstrating how simulation and analysis tools are indispensable for optimizing designs to achieve peak functional and performance efficiency.

Technical (Online) Session on Design. Verify. Innovate: Discover the Power of Analog Design

This Session covers a high-level understanding on Analog IP design flow right from designing transistor level schematics, enabling accurate circuit behaviour analysis, verification, and optimization before fabrication using industry standard EDA tools.

Technical (Online) Session on Fusion Compiler Session by Synopsys Team

The Session will cover the following topics:

• Introduction to VLSI
• VLSI Design flow & Inputs used
• Fusion Compiler Synthesis Flow
• DFT - Design for Test
• Fusion Compiler P&R Flow
• Optimization technologies that deliver the best PPA / QoR
• Signoff checks and Tools (Formality, ICV, STARRC, PT)
• Demo