Home Upcoming Sessions-2024

Upcoming Training Sessions organized by ChipIN Centre under C2S Programme

# TOPIC SESSION DETAILS PRESENTER DATE NO. OF ATTENDEES FEEDBACK
1

Technical (Online) session on SCL 180nm PDK and its integration into the design flow.

During this technical session, participants will have the opportunity to clarify their doubts and queries related to SCL PDK.

ChipIN / SCL 03-June-2024 134
2

Technical (Online) Session on accessing and using Xilinx Alveo U 55C and VCK5000 Versal FPGA Boards.

Introduction to Xilinx Platforms, Intro to Vitis for Acceleration Platforms, Vitis Tool Flow, Vitis Design Analysis, Alveo U55C High Performance Compute Card, VCK5000 Versal Development Card etc.

CoreEL / Xilinx 04-June-2024 89
3

Technical (Online) Session on Introduction to Keysight ADS and Schematic Software

Introductory session on Keysight ADS and Schematic EDA Software.

Keysight 05-June-2024 47
4

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Writing/Defining timing constraints for Async. FIFO Design, TCL scripting for Synthesis, and Genus Synthesis Tool Flow

ChipIN Team 06-June-2024 72
5

Technical (Online) Sessions on Synthesis and Post Synthesis Flow by ChipIN Team

Logic Equivalence Check, post synthesis simulations, zero delay simulation, unit delay simulation and sdf simulations using Xcelium Tool

ChipIN Team 07-June-2024 40
6

Technical Session on Questa simulator and Linting - Day 1

Questa Sim Introduction (Features & Flows), Questa Sim usage in GUI, Command line & in-built examples demo, Questa Sim Advanced features discussion, Advanced GUI -Coverage, Debug etc.

Siemens EDA 10-June-2024 47
7

Technical Session Questa simulator and Linting - Day 2

Introduction to Questa Design solutions and Introduction to Linting, Questa Lint, Methodologies and goals, Advanced Features, Demo and Graphical user interface, Queries etc.

Siemens EDA 11-June-2024
8

Ansys Technical Session on Totem EDA Tool

The session will cover Totem Platform Overview, Totem Static Analysis, Totem Dynamic Analysis, Analysis, IP Model Creation, GUI Wizard etc.

M/s Ansys 13-June-2024
9

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 1

The Session Covers the Start of Physical Design: Import, Floorplan, IO fillers, and Power plan, creation of IO assignment file, MMMC file (GUI + Script) using Innovus Tool

ChipIN Team 19-June-2024
10

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 2

The session covers the Placement, Clock Tree Synthesis and STA: Placement, Creation of Clock tree spec file, CTS (Cluster, trial and full mode) and ECO to fix STA if any

ChipIN Team 20-June-2024
11

Technical (Online) Sessions on Physical Design Flow by ChipIN Team - Day 3

The session will cover the Routing, std. cell fillers and Sign-off, ECO post route and sign-off, Post Route netlist simulations, zero delay simulation, unit delay simulation, back annotation with sdf

ChipIN Team 21-June-2024
12

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 1

The session will cover Custom Compiler Overview, Library Manager, Schematic Editor, Symbol Creation etc.

Synopsys 24-June-2024
13

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 2

The session will cover PrimeWave Design Environment and Simulation etc.

Synopsys 25-June-2024
14

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 3

The session will cover PrimeSim Continuum

Synopsys 26-June-2024
15

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 4

The session will cover Layout Editor, SDL.

Synopsys 27-June-2024
16

Technical (Online) Sessions on Analog Mixed Design Flow by Synopsys Team - Day 5

The session will cover Physical Verification and Parasitic Extraction

Synopsys 28-June-2024

Content owned & provided by Ministry of Electronics & Information Technology, Government of India

Copyright © 2023