Online Interactive Session on Solvnet Helpdesk by Synopsys Team- Reg.

The Session will cover the following topic's:

• How to register on SolvNet.
• Locating the SITE ID on SolvNet.
• How to raise a support ticket on SolvNet for various issues (e.g., tool download, tool features related, design support related, etc.)
• Accessing documentation for any Synopsys product on SolvNet.
• Locating tool binaries, SCL, and other related resources.
• Accessing SAED PDKs.
• Finding training content (including self-paced and university curriculum modules)

Technical (Online) Session on PCB Designing by Cadence Team

The Session details will be shared shortly

Technical (Online) Session on Design Closure Techniques - STA and Timing Closure in Vivado - Day 1

The Session will cover the following topic's:

• Introduction to Static Timing Analysis
• Timing Paths - Reg to Reg path, Input to Reg path, Reg to Output paths
• Clock Variations and Uncertainties
• Static Timing Analysis - Setup and Hold check (Equations)
• Analyzing Timing Reports
• Introduction to AMD Design Constraints
• AMD Performance Baselining Flow for Timing Closure
• Lab1 : Baselining Flow : Apply clock constraints, IO Constraints
• Lab2 : Timing Constraints Wizard usage ( to apply clock constraints, IO constraints, virtual clock)

Technical (Online) Session on Design Closure Techniques - STA and Timing Closure in Vivado - Day 2

The Session will cover the following topic's:

• Multicycle Paths and False Paths /Timing Exceptions
• Lab1: Lab to demonstrate how to constrain Multicycle paths and False paths
• Synthesis Techniques: Pipelining, resource sharing and register duplication
• Lab2: Applying Pipelining for improving design performance
• Implementation Techniques: Incremental Compile, Physical Optimization and Floor planning
• Lab3: Incremental Compile for improving your design response time

Technical (Online) Session on Design Closure Techniques - STA and Timing Closure in Vivado - Day 3

The Session will cover the following topic's:

• Introduction to Floorplanning and Placement blocks (pblocks)
• Lab1: Floorplanning a complex design using pblocks
• Lab2: Understand the physical optimization technique for timing closure
• Clock groups and Clock Domain Crossing concepts
• Synchronization Techniques - Addressing Metastability issues using Single bit Metastability resolution circuits and Asynchronous FIFO
• Lab3: Clock Domain Crossing and Synchronization circuits (Report CDC and apply ASYNC_REG property in your design)

Technical (Online) Session on "DIR-V VEGA Microprocessor based SoC design"

The Session will cover the following topic's:

• Overview of fundamental concepts of RISC-V Instruction Set Architecture (ISA).
• Various processor variants available within the RISC-V ecosystem, along with the range of peripheral IPs typically integrated into SoC designs, Insights into the typical architecture of VEGA-based SoCs and their integration methodology.
• Design and verification processes followed for VEGA SoCs, including validation strategies and methodologies to ensure reliable and robust SoC development.

Two- Days Technical (Online) Session on Low-Power RTL Synthesis Flow using Cadence EDA Tools

Day 1

Session-1: Joules Power Calculator (2:00 PM - 3:30 PM)

• Introduction to Cadence Joules RTL Power Solution
• Estimating the Power and Joules Power Reduction Techniques
• Genus-Joules Integration

Session-2: Low-Power Specification Format (3:45 PM - 5:30 PM)

• Low-power concepts and strategies
• Implement a power switch
• Debugging Design Scenarios

Two- Days Technical (Online) Session on Low-Power RTL Synthesis Flow using Cadence EDA Tools

Day 2

Session-3: Genus Low-Power Synthesis Flow (2:00 PM - 3:30 PM)

• Low-Power Synthesis Flow
• Power Reduction
• Low-Power Methodologies: MSV, PSO, and DVFS

Session-4: Low-Power Synthesis Flow with Genus Stylus (3:45 PM - 5:30 PM)

• Troubleshooting Low-Power Design
• Checking a Low-Power Design with Conformal Software
• Genus-Joules Integration