Two-Days Workshop on Questa Static Formal verification solutions by CoreEL Team - Day 1

The session details are as follows:

• Introduction to FPGA tool flow
• Position of Siemens EDA Formal tools in FPGA tool flow
• Need for Early Verification
• Formal Adaptation
• Overview of Questa Formal tools
• Intro to Questa Lint
• Lint Workflow
• Why is Lint Necessary?
  • Checks
  • Methodology and Goals
• Questa Result Analysis
• Tool Demonstration
• Intro to Questa Autocheck
  • Autocheck Workflow
  • Predefined Checks for Common Problems
  • Autocheck Benefits
  • Autocheck Status Flow
• Questa results Analysis
• Tool Demonstration
• Intro to Questa Covercheck
  • Workflow
  • CoverCheck Benefits
  • Checks for Coverage Exclusions
  • Questa CoverCheck with QuestaSim
• Tool Demonstration
• Intro to Questa CDC
  • CDC Workflow
  • Need for CDC Verification
  • Common CDC Issues
  • Analysis and Debugging
• Tool Demonstration

Two-Days Workshop on Questa Static Formal verification solutions by CoreEL Team - Day 2

The session details are as follows:

• Intro to Questa PropCheck
• PropCheck Workflow
  • Property Checking Methodology
  • Common Use Cases
  • Result Analysis
• Tool Demonstration
• Intro to X-Check
• X-Propagation Challenges
• X-Check Methodology
• Debugging Techniques
• Tool Demonstration
• Intro to Questa Equivalent Check
• Equivalence Checking Workflow
  • Functional and Structural Comparisons
  • Debugging and Result Analysis
• Tool Demonstration

Technical (Online) Session on Automating Digital Implementation with Cadence: Foundational Flow & Stylus CUI - Day 1

The session details are as follows:

Session 1: Introduction to Foundational Flow (2:00 PM - 3:30 PM)

• Overview of Digital Implementation Flow
• Introduction to Flat, Hierarchical, and ILM Flows
• Basic Project Setup:
  • Technology Files
  • Libraries
  • Constraints
• Hands-on: Running Flat Design Flow

Session 2: Hierarchical and ILM Flow in Cadence (3:45 PM - 5:15 PM)

• Understanding Hierarchical Design
• ILM Flow:
  • Purpose
  • Generation
  • Usage
• Setting up a Hierarchical Flow
• Hands-on: Creating and Using ILM Models

Technical (Online) Session on Automating Digital Implementation with Cadence: Foundational Flow & Stylus CUI - Day 2

Session 3: Stylus CUI and Customization (2:00 PM - 3:30 PM)

• Introduction to Stylus Common User Interface (CUI)
• Differences Between Traditional and Stylus CUI
• Setting up a Stylus Environment
• Hands-on: Running Stylus CUI-based Flow

Session 4: Digital Flow Considerations & Best Practices (3:45 PM - 5:15 PM)

• Comparative Analysis of Flat, Hierarchical, and Stylus CUI Flows
• TCL Scripting and Automation
• Hands-on: Customization and Execution of Demo design with ASAP 7nm
• Q&A and Concluding Remarks

Technical (Online) Session on Silvaco EDA UTMOST4, Gateway, SmartSpice & Expert EDA Tools by M/s Silvaco

The session details are as follows:

• UTMOST4 - SPICE Model Extraction (10:00 AM - 10:45 AM)
• Gateway - Schematic Editor and SmartSpice - Simulator (10:45 AM - 11:30 AM)
• Expert - Layout Editor and Smart DRC/LVS (11:30 AM - 1:00 PM)