Technical (Online) Session on ATPG-based DFT flow using Cadence EDA Tool by Entuple Team - Day 1

The Session will cover the following topics:

Session-1:

• Overview of DFT and Cadence Modus DFT Solutions
• Design considerations and ATPG features in Modus
• Tool Demo: Setting up and run Modus ATPG Tool Flow

Session-2:

• Build and verify test structures
• Generating and writing test vectors
• Tool Demo: ATPG Vectors generation

Technical (Online) Session on ATPG-based DFT flow using Cadence EDA Tool by Entuple Team - Day 2

The Session will cover the following topics:

Session-3:

• Scan Chains Debugging
• Broken Scan Chains Analysis
• Tool Demo: Debugging with GUI/ TCL Interf

Session-4:

• Analyzing Sequence
• Debugging Test Pattern
• Tool Demo: Test vectors Simulation using Xcelium

Technical (Online) Session on Getting Started with Altium Designer by Renesas and Altium Team

This session walks you through accessing and activating Altium Designer licenses, with step-by-step instructions for both students and educators. Learn how to:

• Request and activate your Altium Designer license
• Navigate the registration and activation process
• Avoid common setup issues and delays

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Technical (Online) Session on Getting Started with QuickConnect Studio by Renesas and Altium Team

This session teaches students and educators how to set up QuickConnect Studio and educators to request for QuickConnect Kits for hands-on, project-based learning in embedded systems. Learn how to:

• Create a QuickConnect account and access the platform
• Guide educators to request for QuickConnect kits using form
• Navigate the QuickConnect Studio's interface and workflows

The session concludes with a live Q&A to answer your questions. For Course Enrollment: https://www.altium.com/education/cdac

Two Days Technical (Online) session on Questa Static Formal verification solutions by CoreEL Team - Day 1

The Session will cover the following topics:

• Introduction to Questa Inspect
• Inspect Workflow
• Predefined Checks for Common Problems
• Inspect Benefits
• Inspect Status Flow
• Questa results Analysis
• Hands on Tool Demonstration

Two Days Technical (Online) session on Questa Static Formal verification solutions by CoreEL Team - Day 2

The Session will cover the following topics:

• Intro to Questa Increase coverage and Workflow
• Increase coverage Benefits
• Checks for Coverage Exclusions
• Questa Increase coverage with Questa Sim
• Hands on Tool Demonstration

Technical (Online) Session on "VEGA Processors: India's Indigenous RISC-V Based Computing Revolution"

This session will introduce the core principles of the RISC-V Instruction Set Architecture (ISA) and explore the different processor variants within the RISC-V ecosystem. It will also discuss the range of peripheral IPs commonly integrated into SoC designs. Participants will gain an understanding of the architecture and integration approach of VEGA-based SoCs, as well as the design and verification processes adopted for these systems. The session will further highlight the validation strategies and methodologies employed to ensure dependable and high-quality SoC development.