Technical (Online) Session on Design and Simulation of Electronic Circuits with PCB Implementation

The Session may cover the following topic's (Agenda):

1. Electronic Product Design Cycle
2. Design Entry (Schematic): Design Example - Hands On Working with projects and its configuration, Parts Manager, Add parts in parts manager, Search the parts - Global/Local Search Parts placements, Wiring your circuits: Auto/Manual/Virtual Wiring, Annotate your circuit, Property Editor: Parts/Pins/Nets
3. Predict the behavior of your circuit: Circuit Simulation - Hands On Setting up your circuit for simulation and netlist generation, Verify circuit parameters using Interactive waveform viewer, Measurement Functions, Types of Analysis, DC Bias Point Analysis : Bias point display, DC Analysis : DC Sweep, AC Analysis : AC Sweep, Transient/Time Domain Analysis, Parametric Sweep
4. Generate the BOM (Bill of Material)
5. Introduction to PCB and Layout Design Process: -Hands On Prepare your circuit for layout design,Package Mapping and netlist generation for Layout design, Design stackup and Layout configuration (Floor planning), Create board outline and Package Keep out area, Introduction to Industry Standards, Component Placement and Alignment, Placement techniques : Understand the, importance of parts placement in Layout, Auto Placement/Manual, Component Alignment, Define spacing constraint b/w component to component and component to obstacle Constraint Manager.

Four Days Technical (Online) Session on SystemVerilog Assertions, Controlling SV Assertions, Constraints handling by Synopsys Team - Day 1

The Session details will be shared shortly.

Four Days Technical (Online) Session on SystemVerilog Assertions, Controlling SV Assertions, Constraints handling by Synopsys Team - Day 2

The Session details will be shared shortly.

Four Days Technical (Online) Session on SystemVerilog Assertions, Controlling SV Assertions, Constraints handling by Synopsys Team - Day 3

The Session details will be shared shortly.

Four Days Technical (Online) Session on SystemVerilog Assertions, Controlling SV Assertions, Constraints handling by Synopsys Team - Day 4

The Session details will be shared shortly.

Technical (Online) Session on Silvaco EDA UTMOST4, Gateway, SmartSpice & Expert EDA Tools by M/s Silvaco

The Session may cover the following topic's (Agenda):

• UTMOST4 - SPICE Model Extraction
• Gateway - Schematic Editor and SmartSpice - Simulator
• Expert - iPDK Flow

Interactive Online Session on Siemens Questa Sim EDA Tool

The Session may cover the following topic's (Agenda):

• Introduction to QuestaSim: Overview and Capabilities
• QuestaSim Setup and Configuration
• Graphical User Interface (GUI) Navigation
• Project Initialization and Configuration
• Compilation and Analysis of Design Files
• Simulation & Code Coverages
• Interactive Q&A