Technical (Online) Session on Calibre EDA Tool - Day 1

The Session will cover the following topics:

Session 1: Introduction to Physical and Circuit Verification

• Importance of physical verification
• Intro to Calibre nmDRC, nmLVS, and PEX

Session 2: Using Calibre nmDRC/nmLVS

• Calibre basic concepts
• Running jobs using Calibre GUI
• Intro to Calibre RVE
• Calibre DRC process flow
• nmDRC HTML Reports
• Rule recipe customization
• Waiving and fixing results
• RVE features & LVL options

Technical (Online) Session on Calibre EDA Tool - Day 2

The Session details will cover the following topics:

Session 3: Calibre nmLVS Basics

• LVS process flow
• Job execution
• Texting & connectivity
• Troubleshooting shorts/opens
• Antenna & ERC checks

Session 4: Calibre Interactive - Advanced Features

• Interactive DRC/LVS
• Cell preservation
• Hierarchical cell analysis

Session 5: Calibre Parasitic Extraction (Calibre xRC)

• Parasitic network basics
• xRC netlist extraction & Calibre xRC flow
• Using RVE/DESIGNrev
• Reduction techniques

Technical (Online) Session: An Introduction to Physical Verification by Siemens EDA

The Session will cover the following topics:

• Master physical verification methodologies
• Implement efficient LVS comparison techniques
• Efficiently using Layout Viewing tool
• Using Calibre Interactive for Job Submission
• Improving Debug capabilities using Calibre RVE

Technical (Online) Session on Seamless RF Design using Cadence AWR

The Session will cover the following topics:

• RF Basics
• RF Applications
• RF designs using AWR

Technical (Online) Session on Hardware Emulation & Chip Validation by Siemens EDA

The Session will be shared shortly

Technical (Online) Session: An Introduction to Physical Design Implementation by Siemens EDA

The Session will cover the following topics:

• Describe end-to-end Physical Design flow
• Identify standard inputs and outputs for Physical Design
• Explain the processes of Placement, Clock Tree Synthesis (CTS), and Routing using Aprisa
• Understand PPA (Power, Performance, Area) constraints and Signoff procedures

Technical (Online) Session on Advanced DFT Features Using Cadence EDA Tools by Entuple Team - Day 1

The Session details will cover the following topics:

Session 1:

• Overview of DFT and advanced features in Cadence EDA tools
• Boundary Scan & Programmable Memory Built-In Self-Test (PMBIST)
• Demo: Setting up and running PMBIST

Session 2:

• Scan Compression techniques for reducing test data volume and test time
• Key configuration and flow setup
• Demo: Setting up and running Scan Compression

Technical (Online) Session on Advanced DFT Features Using Cadence EDA Tools by Entuple Team - Day 2

The Session details will cover the following topics:

Session 3:

• On-Product Clock Generation (OPCG) for at-speed test
• Defining and inserting the OPCG Macro
• Demo: Setting up and running OPCG

Session 4:

• Logic Built-In Self-Test (LBIST): Pattern generation for self-test
• Design considerations and flow
• Demo: Setting up and running LBIST